1. Field of the Invention
The invention relates to a circuit configuration for a frequency divider including a prescaler with at least four different division ratios, a main counter disposed at an output of the prescaler and having an adjustable division ratio, and a lower-level first swallow counter having an adjustable division ratio and being able to change the division ratio of the prescaler.
A similar circuit configuration which is the closest prior art is known from German Published, Non-Prosecuted Patent Application DE 197 00 017 A1. That document describes, in general form, a PLL frequency synthesizer circuit which contains a comparison frequency divider that is equipped with a dual modulus prescaler and a swallow counter. The circuit has a modulus signal output controller which controls the dual modulus prescaler.
One problem with that known circuit configuration is that, when the dual modulus principle is used for a synthesizer, digital broadband radio systems require a low prescaler ratio in order to permit the overall required division ratios to be achieved. However, in a system such as that, small prescaler ratios mean large main divider ratios, which lead to a high main divider operating frequency and thus to high current consumption and poor system characteristics, such as phase noise.
It is accordingly an object of the invention to provide a circuit configuration for a frequency divider, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which manages with a high prescaler ratio and a low main divider ratio in order to achieve a low overall division ratio N.
The invention is based upon the discovery that, in order to achieve a low overall division ratio N with a high prescaler ratio and a low main divider ratio at the same time, it is possible to use a number of swallow counters instead of a single swallow counter. Each swallow counter counts in a multidigit counting system in conjunction with a dual modulus divider and can thus generate a high overall division ratio with low individual division ratios throughout.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for a frequency divider, comprising a prescaler having at least two different division ratios, at least two further different division ratios, and an output; a main counter connected to the output of the prescaler and having an adjustable division ratio and an output; a first lower-level swallow counter for changing the division ratio of the prescaler, the first swallow counter having an adjustable division ratio; and at least one second lower-level swallow counter for changing a division ratio of the prescaler between the two further division ratios, the at least one second lower-level swallow counter connected to the output of the main counter and having an adjustable division ratio.
In accordance with another feature of the invention, the prescaler has two dual modulus dividers which can both be changed through the swallow counters at least between division ratios K1 and K1+1 as well as K2 and K2+1, a first changeover input for changing the division ratio K1 of the first dual modulus divider to K1+1, a second input for changing the division ratio K2 of the second dual modulus divider to K2+1, and an additional circuit is provided between the two dual modulus dividers resulting in the first dual modulus divider being changed to a higher division ratio K1+1 only once within one counting run of the second dual modulus divider.
As a rule, the division ratios K1 and K2 are numbers which are calculated as powers to base 2, where K1=2p1 and K2=2P2. The overall division ratio of the prescaler (prescaler division ratio) Ptot is given by:
Ptot=2P2* 2P1+2p1*mc1+mc2,
where P1 is the exponent of 2 for the division ratio of the first dual modulus divider, P2 is the exponent of 2 for the division ratio of the second dual modulus divider and mc2 and mc1 are the values 0 or 1 of the changeover inputs (mc) of the respective dual modulus divider. In the case of the exponents P2 and P1, it is advantageous for P2xe2x89xa6P1 and, preferably, for 2P1=2P2. Thus, the variation of the values mc0 and mc1 gives the following possible prescaler division ratios:
Ptot=2(P2+P1)+2p1*0+0,
Ptot=2(P2+P1)+2p1*0+1,
Ptot=2(P2+P1)+2p1*1+0,
and
Ptot=2(P2+P1)+2p1*1+1.
Thus, for example, if a 16/17 divider is used as the first dual modulus divider and a 4/5 divider is used as the second dual modulus divider, this results in the following possible prescaler division ratios for the quadro modulus divider:
xe2x80x83Ptot=2(2+4)+24*0+0=64,
Ptot=2(2+4)+24*0+1=65,
Ptot=2(2+4)+24*1+0=80,
and
Ptot=2(2+4)+24*1+1=81.
In accordance with a further feature of the invention, the main counter can be configured in such a way that, once M preset pulses have been input, it emits an output pulse and automatically resets itself to a predetermined initial value once again.
In accordance with an added feature of the invention, the input of the first adjustable swallow counter can be connected to the output of the prescaler, and the output of the swallow counter can be connected to the lower value changeover input of the quadro modulus prescaler (=changeover input of the first dual modulus divider), with the loading pulse of the main counter also resetting the first swallow counter. Furthermore, the input of the second adjustable swallow counter can be connected to the output of the prescaler, and the output of the second swallow counter can be connected to the higher value changeover input of the quadro modulus prescaler (=changeover input of the second dual modulus divider), with the loading pulse of the main counter also resetting the second swallow counter.
This circuit configuration results in an overall division ratio N for the overall circuit configuration of N=(K1*K2)*M+K2*A2+A1. Through skilful selection of the individual division ratios, a division ratio which is high overall can easily be achieved by using intrinsically small individual division ratios. In principle, this type of division process corresponds to the notation for a large number in a numerical system with small base numbers by the use of a number of xe2x80x9cdigitsxe2x80x9d. In this case, however, due to the circuit configuration, all of the overall division ratios can only be defined in steps of 1 from a specific value N1.
In accordance with an additional feature of the invention, the first dual modulus divider is a 16/17 divider, the second dual modulus divider is a 4/5 divider, and the two form a quadro modulus prescaler with division ratios 64/65/80/81. This results in an overall division ratio of N=64*M+16*A2+A1. All of the integer overall division ratios Nxe2x89xa7960 from Mxe2x89xa715 can be selected by using 0xe2x89xa6A1, A2xe2x89xa6M, without any gaps, by variation of the M, A1 and A2 values.
In accordance with yet another feature of the invention, the first and the second dual modulus dividers are each an 8/9 divider, and the two form a quadro modulus prescaler with division ratios 64/65/72/73.
In accordance with yet a further feature of the invention, the first and the second dual modulus divider are each a 16/17 divider, and the two form a quadro modulus prescaler with division ratios 256/257/272/273.
In accordance with yet an added feature of the invention, the division ratio K1 of the first dual modulus divider is equal to the division ratio K2 of the second dual modulus divider. This avoids redundancies in the numbering of the divider.
In accordance with yet an additional feature of the invention, in order to provide a particularly low overall division ratio N with prescaler ratios that are as high as possible, the prescaler has other interconnected dual modulus dividers and further swallow counters are provided, with each of the dual modulus dividers being assigned a swallow counter and with there being an additional circuit between the dual modulus dividers which results in the other dual modulus dividers being changed to the higher division ratio only once within a counting run of the further dual modulus divider. In this way, by using a xe2x80x9cmultidigitxe2x80x9d overall divider, a corresponding high overall division ratio N can be achieved through the use of a small number of low-value dual modulus dividers.
In accordance with a concomitant feature of the invention, the circuit configurations can be included as frequency dividers in a phased locked loop (PLL) circuit. This PLL circuit according to the invention can then be used in a particularly preferred manner in a mobile radio system, resulting in considerable current savings in comparison with the prior art, as a result of which, in turn, the current sources (rechargeable batteries) which are used can also be reduced in size without reducing the available operating time.
It is self-evident that the features of the invention which are mentioned above and which will be explained in more detail in the following text can be used not only in the respective described combination but also in other combinations or on their own without departing from the scope of the invention.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for a frequency divider, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.